B2.93 Secure Debug Enable Register, EL3
The SDER32_EL3 characteristics are:
Purpose
Allows access to the AArch32 register SDER only from AArch64 state. Its value has no effect
on execution in AArch64 state.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
SDER32_EL3 is architecturally mapped to AArch32 register SDER. See B1.107 Secure Debug
Enable Register on page B1-337.
Attributes
SDER32_EL3 is a 32-bit register.
31
0
RES0
SUNIDEN
SUIDEN
12
Figure B2-64 SDER32_EL3 bit assignments
[31:2]
Reserved, RES0.
SUNIDEN, [1]
Secure User Non-invasive Debug Enable The possible values are:
0 Non-invasive debug not permitted in Secure EL0 mode. This is the Warm reset value.
1 Non-invasive debug permitted in Secure EL0 mode.
SUIDEN, [0]
Secure User Invasive Debug Enable. The possible values are:
0 Invasive debug not permitted in Secure EL0 mode. This is the Warm reset value.
1 Invasive debug permitted in Secure EL0 mode.
To access the SDER32_EL3:
MRS <Xt>, SDER32_EL3 ; Read SDER32_EL3 into Xt
MSR SDER32_EL3, <Xt> ; Write Xt to SDER32_EL3
B2 AArch64 system registers
B2.93 Secure Debug Enable Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-535
Non-Confidential
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