ARM Cortex-A35 User Manual

C2.4 PMU interrupts
The processor asserts the nPMUIRQ signal when an interrupt occurs that the PMU generated.
You can route this signal to an external interrupt controller for prioritization and masking. It is the only
mechanism that signals this interrupt to the processor.
This interrupt is also driven as a trigger input to the CTI.
Related information
C4.2 Cross-trigger inputs and outputs on page C4-605
C2 PMU
C2.4 PMU interrupts
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English