ARM Cortex-A35 User Manual

Table C2-3 Performance monitoring events (continued)
Number Event mnemonic PMU event
bus to
external
PMU
event bus
to trace
Event name
0xE6
- - -
Attributable Performance Impact Event.
Counts every cycle there is an interlock that is because
of an Advanced SIMD or floating-point instruction.
Stall cycles because of a stall in the Wr stage, typically
awaiting load data, are excluded.
0xE7
- - -
Attributable Performance Impact Event
Counts every cycle there is a stall in the Wr stage
because of a load miss.
0xE8
- - -
Attributable Performance Impact Event.
Counts every cycle there is a stall in the Wr stage
because of a store.
- - [26] [26] L2 (data or tag) memory error, correctable or non-
correctable.
- - [27] [27] SCU snoop filter memory error, correctable or non-
correctable.
- - [28] - Advanced SIMD and floating-point retention active.
- - [29] - Core retention active.
C2 PMU
C2.3 Performance monitoring events
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C2-591
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English