ARM Cortex-A35 User Manual

Table C2-3 Performance monitoring events (continued)
Number Event mnemonic PMU event
bus to
external
PMU
event bus
to trace
Event name
0xCB
- - - Indirect branch that is mispredicted because of address
miscompare.
0xCC
- - - Conditional branch that is mispredicted.
0xD0
- [23] [23] L1 Instruction Cache (data or tag) memory error.
0xD1
- [24] [24] L1 Data Cache (data, tag, or dirty) memory error,
correctable or non-correctable.
0xD2
- [25] [25] TLB memory error.
0xE0
- - -
Attributable Performance Impact Event.
Counts every cycle that the DPU IQ is empty and that is
not because of a recent micro-TLB miss, an instruction
cache miss or a pre-decode error.
0xE1
- - -
Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty and there is an
instruction cache miss being processed.
0xE2
- - -
Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty and there is an
instruction micro-TLB miss being processed.
0xE3
- - -
Attributable Performance Impact Event.
Counts every cycle the DPU IQ is empty and there is a
pre-decode error being processed.
0xE4
- - -
Attributable Performance Impact Event.
Counts every cycle there is an interlock that is not
because of an Advanced SIMD or floating-point
instruction, and not because of a load/store instruction
waiting for data to calculate the address in the AGU.
Stall cycles because of a stall in Wr, typically awaiting
load data, are excluded.
0xE5
- - -
Attributable Performance Impact Event.
Counts every cycle there is an interlock that is because
of a load/store instruction waiting for data to calculate
the address in the AGU.
Stall cycles because of a stall in Wr, typically awaiting
load data, are excluded.
C2 PMU
C2.3 Performance monitoring events
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C2-590
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English