ARM Cortex-A35 User Manual

Table C2-3 Performance monitoring events (continued)
Number Event mnemonic PMU event
bus to
external
PMU
event bus
to trace
Event name
0x14
L1I_CACHE [18] [18] L1 Instruction cache access.
0x15
L1D_CACHE_WB [19] [19] L1 Data cache writeback.
0x16
L2D_CACHE [20] [20] L2 Data cache access.
0x17
L2D_CACHE_REFILL [21] [21] L2 Data cache refill.
0x18
L2D_CACHE_WB [22] [22] L2 Data cache write-back.
0x19
BUS_ACCESS - - Bus access.
0x1A
MEMORY_ERROR - - Local memory error.
0x1B
INST_SPEC - - Operation speculatively executed.
0x1D
BUS_CYCLES - - Bus cycle.
0x1E
CHAIN - - Odd performance counter chain mode.
0x60
BUS_ACCESS_LD - - Bus access - Read.
0x61
BUS_ACCESS_ST - - Bus access - Write.
0x73
DP_SPEC - - Operation speculatively executed, integer data-
processing.
0x74
ASE_SPEC - - Operation speculatively executed, Advanced SIMD
instruction.
0x75
VFP_SPEC - - Operation speculatively executed, floating-point
instruction.
0x77
CRYPTO_SPEC - - Operation speculatively executed, Cryptographic
instruction.
0x7A
BR_INDIRECT_SPEC - - Branch that is speculatively executed - Indirect branch.
0x86
EXC_IRQ - - Exception taken, IRQ.
0x87
EXC_FIQ - - Exception taken, FIQ.
0xC0
- - - External memory request.
0xC1
- - - Non-cacheable external memory request.
0xC2
- - - Linefill because of prefetch.
0xC4
- - - Entering read allocate mode.
0xC5
- - - Read allocate mode.
0xC6
- - - Pre-decode error.
0xC7
- - - Data Write operation that stalls the pipeline because the
store buffer is full.
0xC8
- - - SCU Snooped data from another core for this core.
0xC9
- - - Conditional branch that is executed.
0xCA
- - - Indirect branch that is mispredicted.
C2 PMU
C2.3 Performance monitoring events
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C2-589
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English