A12.1 Bypassing the GIC CPU Interface
The processor optionally implements the GIC CPU Interface. If present, you can disable it by asserting
the GICCDISABLE signal HIGH at reset.
If the GIC is enabled, the input pins nVIRQ and nVFIQ must be tied off to HIGH because the internal
GIC CPU interface generates the virtual interrupt signals to the cores. Software controls the nIRQ and
nFIQ signals, therefore there is no requirement to tie them HIGH. If you disable the GIC CPU interface,
a GIC that is external to the processor can drive the input signals nVIRQ and nVFIQ.
Asserting the GICCDISABLE signal HIGH at reset removes access to the memory-mapped and system
GIC CPU Interface registers.
Related information
B2.54 AArch64 Processor Feature Register 0, EL1 on page B2-450
B1.85 Processor Feature Register 1 on page B1-291
A12 GIC CPU Interface
A12.1 Bypassing the GIC CPU Interface
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A12-142
Non-Confidential
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