B2.28 Configuration Base Address Register, EL1
The CBAR_EL1 characteristics are:
Purpose
Holds the physical base address of the memory-mapped GIC CPU interface registers.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
CBAR_EL1 is a 64-bit register.
63
18 17
0
RES0
40 39
PERIPHBASE[39:18]
RES0
Figure B2-3 CBAR_EL1 bit assignments
[63:40]
Reserved, RES0.
PERIPHBASE[39:18], [39:18]
If the processor is implemented with the GIC CPU interface, the input PERIPHBASE[39:18]
determines the reset value. If the GIC CPU interface is not implemented, this field is RAZ.
[17:0]
Reserved, RES0.
To access the CBAR_EL1:
MRS <Xt>, S3_1_C15_C3_0 ; Read CBAR_EL1 into Xt
Register access is encoded as follows:
Table B2-20 CBAR_EL1 access encoding
op0 op1 CRn CRm op2
11 001 1111 0011 000
B2 AArch64 system registers
B2.28 Configuration Base Address Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-397
Non-Confidential
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