ARM Cortex-A35 User Manual

B2.57 AArch32 Instruction Set Attribute Register 0, EL1
The ID_ISAR0_EL1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_ISAR0_EL1 is architecturally mapped to AArch32 register ID_ISAR0. See
B1.74 Instruction Set Attribute Register 0 on page B1-269.
Attributes
ID_ISAR0_EL1 is a 32-bit register.
31
28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
RES0 Divide Debug Coproc CmpBranch Bitfield BitCount Swap
Figure B2-30 ID_ISAR0_EL1 bit assignments
[31:28]
Reserved, RES0.
Divide, [27:24]
Indicates the implemented Divide instructions:
0x2 • SDIV and UDIV in the T32 instruction set.
• SDIV and UDIV in the A32 instruction set.
Debug, [23:20]
Indicates the implemented Debug instructions:
0x1 BKPT.
Coproc, [19:16]
Indicates the implemented Coprocessor instructions:
0x0 None implemented, except for separately attributed by the architecture including
CP15, CP14, Advanced SIMD and floating-point.
CmpBranch, [15:12]
Indicates the implemented combined Compare and Branch instructions in the T32 instruction
set:
0x1 CBNZ and CBZ.
Bitfield, [11:8]
Indicates the implemented bit field instructions:
B2 AArch64 system registers
B2.57 AArch32 Instruction Set Attribute Register 0, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English