ARM Cortex-A35 User Manual

0x1 BFC, BFI, SBFX, and UBFX.
BitCount, [7:4]
Indicates the implemented Bit Counting instructions:
0x1 CLZ.
Swap, [3:0]
Indicates the implemented Swap instructions in the A32 instruction set:
0x0 None implemented.
To access the ID_ISAR0_EL1:
MRS <Xt>, ID_ISAR0_EL1 ; Read ID_ISAR0_EL1 into Xt
Register access is encoded as follows:
Table B2-49 ID_ISAR0_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0010 000
B2 AArch64 system registers
B2.57 AArch32 Instruction Set Attribute Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-456
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English