B2.79 Memory Attribute Indirection Register, EL3
The MAIR_EL3 characteristics are:
Purpose
Provides the memory attribute encodings corresponding to the possible AttrIndx values in a
Long-descriptor format translation table entry for stage 1 translations at EL3.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
MAIR_EL2 is permitted to be cached in a TLB.
Configurations
MAIR_EL3[31:0] is architecturally mapped to AArch32 registers:
• PRRR (S) when TTBCR.EAE is 0. See B1.101 Primary Region Remap Register
on page B1-322.
• MAIR0 (S) when TTBCR.EAE is 1. See B1.95 Memory Attribute Indirection Registers 0
and 1 on page B1-310.
MAIR_EL3[63:32] is architecturally mapped to AArch32 registers:
• NMRR (S) when TTBCR.EAE is 0. See B1.99 Normal Memory Remap Register
on page B1-319.
• MAIR1 (S) when TTBCR.EAE is 1. See B1.95 Memory Attribute Indirection Registers 0
and 1 on page B1-310.
Attributes
MAIR_EL3 is a 64-bit register.
The MAIR_EL3 bit assignments follow the same pattern as described in B2.77 Memory Attribute
Indirection Register, EL1 on page B2-496.
To access the MAIR_EL3:
MRS <Xt>, MAIR_EL3 ; Read EL3 Memory Attribute Indirection Register
MSR MAIR_EL3, <Xt> ; Write EL3 Memory Attribute Indirection Register
Register access is encoded as follows:
Table B2-73 MAIR_EL3 access encoding
op0 op1 CRn CRm op2
11 110 1010 0010 000
B2 AArch64 system registers
B2.79 Memory Attribute Indirection Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-499
Non-Confidential
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