A2.3 About system control
The system registers control and provide status information for the functions that the processor
implements.
The main functions of the system registers are:
• Overall system control and configuration.
• MMU configuration and management.
• Configuration and management of the L1 and the L2 caches.
• System performance monitoring.
• GIC configuration and management.
The system registers are accessible in the AArch64 and AArch32 Execution states. Some of the system
registers are accessible through the memory-mapped or external debug interfaces. If EL3 is using
AArch32, the CP15SDISABLE2 input disables write access to the following system registers:
• System Control Register (SCTLR).
• Translation Table Base Register 1 (TTBR1).
• Translation Table Base Control Register (TTBCR).
• Domain Access Control Register (DACR).
• Primary Region Remap Register (PRRR).
• Normal Memory Remap Register (NMRR).
• Memory Attribute Indirection Register 0 (MAIR0).
• Memory Attribute Indirection Register 1 (MAIR1).
• Vector Base Address Register (VBAR).
• Monitor Vector Base Address Register (MVBAR).
• Reset Management Register (RMR) at EL3.
• Interrupt Controller Monitor System Register Enable (ICC_MSRE).
• Non-Secure Address Control Register (NSACR).
• Secure Debug Enable Register (SDER).
• Secure Debug Control Register (SDCR).
Related reference
B1.1 AArch32 register summary on page B1-150
B2.1 AArch64 register summary on page B2-362
A2 Technical Overview
A2.3 About system control
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reserved.
A2-46
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