ARM Cortex-A35 User Manual

A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals
The STANDBYWFI[n] signal indicates when an individual core is in idle and low-power state. The
power management controller can remove power from an individual core when STANDBYWFI[n] is
asserted.
The STANDBYWFIL2 signal indicates when all individual cores and the L2 memory system are in idle
and low-power state. A power management controller can remove power from the Cortex‑A35 processor
when STANDBYWFIL2 is asserted. See A4.8 Powering down the processor without system driven L2
flush on page A4-67 and A4.10 Powering down the processor with system driven L2 flush on page A4-69
for more information.
The Cortex‑A35 processor includes a minimal L2 memory system in configurations without an L2 cache.
Therefore, the power management controller must always wait for assertion of STANDBYWFIL2
before removing power from the Cortex‑A35 processor. This applies to configurations that use the mini-
SCU and configurations that use the SCU.
The following figure shows how STANDBYWFI[3:0] and STANDBYWFIL2 correspond to individual
cores and the Cortex‑A35 processor.
Processor
Core 3
Level 2 memory system
Snoop Control Unit (SCU)
STANDBYWFI[3:0] STANDBYWFIL2
Core 2
Core 1
Core 0
Level 1 memory system
Data Processing
Unit (DPU)
Instruction Fetch
Unit (IFU)
Figure A4-4 STANDBYWFI[3:0] and STANDBYWFIL2 signals
A4 Power Management
A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English