C10.14 Performance Monitors Peripheral Identification Register 2
The PMPIDR2 characteristics are:
Purpose
Provides information to identify a Performance Monitor component.
Usage constraints
The accessibility to the PMPIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C2.2 External register access permissions to the PMU registers on page C2-587 describes the
condition codes.
The PMPIDR2 can be accessed through the external debug interface.
Configurations
The PMPIDR2 is in the Debug power domain.
Attributes
See the register summary in C10.9 Memory-mapped PMU register summary on page C10-714.
RES0
31 0
34
DES_1
78
Revision
JEDEC
2
Figure C10-10 PMPIDR2 bit assignments
[31:8]
Reserved, RES0.
Revision, [7:4]
0x3 r1p0.
JEDEC, [3]
0b1 RAO. Indicates a JEP106 identity code is used.
DES_1, [2:0]
0b011 Arm Limited. This is the most significant nibble of JEP106 ID code.
The PMPIDR2 can be accessed through the external debug interface, offset 0xFE8.
C10 PMU registers
C10.14 Performance Monitors Peripheral Identification Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-722
Non-Confidential
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