B1.65 Hyp Instruction Fault Address Register
The HIFAR characteristics are:
Purpose
Holds the virtual address of the faulting address that caused a synchronous Prefetch Abort
exception that is taken to Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Execution in any Non-secure mode other than Hyp mode makes HPFAR UNKNOWN.
Configurations
HIFAR is architecturally mapped to AArch64 register FAR_EL2[63:32]. See B2.45 Fault
Address Register, EL2 on page B2-430.
HIFAR is architecturally mapped to AArch32 register IFAR (S). See B1.86 Instruction Fault
Address Register on page B1-293.
Attributes
HIFAR is a 32-bit register.
31
0
VA of faulting address of synchronous Prefetch Abort exception
Figure B1-21 HIFAR bit assignments
VA, [31:0]
The Virtual Address of faulting address of synchronous Prefetch Abort exception.
To access the HIFAR:
MRC p15, 4, <Rt>, c6, c0, 2 ; Read HIFAR into Rt
MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR
Register access is encoded as follows:
Table B1-50 HIFAR access encoding
coproc opc1 CRn CRm opc2
1111 100 0110 0000 010
B1 AArch32 system registers
B1.65 Hyp Instruction Fault Address Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-252
Non-Confidential
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