ARM Cortex-A35 User Manual

Chapter A4
Power Management
This chapter describes the power domains and the power modes in the Cortex‑A35 processor.
It contains the following sections:
• A4.1 Power domains on page A4-58.
• A4.2 Power modes on page A4-61.
• A4.3 Core Wait for Interrupt on page A4-62.
• A4.4 Core Wait for Event on page A4-63.
• A4.5 L2 Wait for Interrupt on page A4-64.
• A4.6 Powering down an individual core on page A4-65.
• A4.7 Powering up an individual core on page A4-66.
• A4.8 Powering down the processor without system driven L2 flush on page A4-67.
• A4.9 Powering up the processor without system driven L2 flush on page A4-68.
• A4.10 Powering down the processor with system driven L2 flush on page A4-69.
• A4.11 Powering up the processor with system driven L2 flush on page A4-70.
• A4.12 Entering Dormant mode on page A4-71.
• A4.13 Exiting Dormant mode on page A4-72.
• A4.14 Event communication using WFE or SEV on page A4-73.
• A4.15 Communication to the Power Management Controller on page A4-74.
• A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals on page A4-75.
• A4.17 Q-channel on page A4-76.
100236_0100_00_en
Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A4-57
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English