C8.10 External Debug Peripheral Identification Register 1
The EDPIDR1 characteristics are:
Purpose
Provides information to identify an external debug component.
Usage constraints
This register is accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table C1-1 Conditions on external register access to debug registers on page C1-579 describes
the condition codes.
Configurations
The EDPIDR1 is in the Debug power domain.
Attributes
See C8.1 Memory-mapped debug register summary on page C8-644.
RES0
31 0
34
Part_1
78
DES_0
Figure C8-8 EDPIDR1 bit assignments
[31:8]
Reserved, RES0.
DES_0, [7:4]
0xB Arm Limited. This is the least significant nibble of JEP106 ID code.
Part_1, [3:0]
0xD Most significant nibble of the debug part number.
The EDPIDR1 can be accessed through the external debug interface, offset 0xFE4.
C8 Memory-mapped debug registers
C8.10 External Debug Peripheral Identification Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C8-659
Non-Confidential
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