ARM Cortex-A35 User Manual

C6.2 Debug Breakpoint Control Registers
The DBGBCRn characteristics are:
Purpose
Holds control information for a breakpoint. Each DBGBVR is associated with a DBGBCR to
form a Breakpoint Register Pair (BRP). DBGBVRn is associated with DBGBCRn to form
BRPn.
The range of n for DBGBCRn is 0 to 5.
Usage constraints
These registers are accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
DBGBCRn are architecturally mapped to:
• The AArch64 DBGBCRn_EL1 registers. See C7.2 Debug Breakpoint Control Registers,
EL1 on page C7-636.
• The external DBGBCRn registers.
Attributes
See C6.1 AArch32 debug register summary on page C6-620.
The debug logic reset value of a DBGBCRn is UNKNOWN.
31 24 23 20 19 16 15 13 9 8 5 4 3 2 1 0
LBN RES0SSC
12
HMC
14
BT BAS PMC ERES0 RES0
Figure C6-1 DBGBCR
[31:24]
Reserved, RES0.
BT, [23:20]
Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This
includes the meaning of the value held in the associated DBGBVRn, indicating whether it is an
instruction address match or mismatch or a Context match. It also controls whether the
breakpoint is linked to another breakpoint. The possible values are:
0b0000 Unlinked instruction address match.
0b0001 Linked instruction address match.
0b0010 Unlinked Context ID match.
0b0011 Linked Context ID match.
0b0100 Unlinked instruction address mismatch.
0b0101 Linked instruction address mismatch.
0b1000 Unlinked VMID match.
0b1001 Linked VMID match.
C6 AArch32 debug registers
C6.2 Debug Breakpoint Control Registers
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C6-622
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English