Table C6-1 AArch32 debug register summary (continued)
CRn Op2 CRm Op1 Name Type Description
c0 6 c2 0 DBGWVR2 RW Debug Watchpoint Value Register 2
c0 6 c3 0 DBGWVR3 RW Debug Watchpoint Value Register 3
c0 7 c0 0 DBGWCR0 RW C6.3 Debug Watchpoint Control Registers on page C6-625
c0 7 c1 0 DBGWCR1 RW
c0 7 c2 0 DBGWCR2 RW
c0 7 c3 0 DBGWCR3 RW
c1 0 c0 0 DBGDRAR[31:0] RO Debug ROM Address Register
- - c1 - DBGDRAR[63:0] RO
c1 1 c4 0 DBGBXVR4 RW Debug Breakpoint Extended Value Register 4
c1 1 c5 0 DBGBXVR5 RW Debug Breakpoint Extended Value Register 5
c1 4 c0 0 DBGOSLAR WO Debug OS Lock Access Register
c1 4 c1 0 DBGOSLSR RO Debug OS Lock Status Register
c1 4 c3 0 DBGOSDLR RW Debug OS Double Lock Register
c1 4 c4 0 DBGPRCR RW Debug Power/Reset Control Register
c2 2 c0 0 DBGDSAR[31:0] RO
Debug Self Address Register RES0
Previously defined the offset from the base address defined in DBGDRAR
of the physical base address of the debug registers for the processor. This
register is now deprecated and RES0.
- 0 c2 - DBGDSAR[63:0] RO
c7 7 c0 0 DBGDEVID2 RO Debug Device ID Register 2, RES0
c7 7 c1 0 DBGDEVID1 RO C6.6 Debug Device ID Register 1 on page C6-632
c7 7 c2 0 DBGDEVID RO C6.5 Debug Device ID Register on page C6-630
c7 6 c8 0 DBGCLAIMSET RW Debug Claim Tag Set Register
c7 6 c9 0 DBGCLAIMCLR RW Debug Claim Tag Clear Register
c7 6 c14 0 DBGAUTHSTATUS RO Debug Authentication Status Register
C6 AArch32 debug registers
C6.1 AArch32 debug register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C6-621
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