ARM Cortex-A35 User Manual

A9.2 ACE configurations
This section describes the ACE configurations.
Note
If you want to connect the processor to an AXI interconnect, Arm recommends that you use the AXI
processor configuration option. Using the ACE processor configuration option in AXI mode is less area-
efficient than the AXI configuration option.
Table A9-1 Supported ACE configurations
Signal Feature
AXI
mode
ACE non-coherent ACE outer coherent ACE inner coherent
No L3
cache
With L3
cache
No L3
cache
With L3
cache
No L3
cache
With L3
cache
BROADCASTCACHEMAINT 0 0 1 0 1 0 1
BROADCASTOUTER 0 0 0 1 1 1 1
BROADCASTINNER 0 0 0 0 0 1 1
The following table shows the key features in each of the supported ACE configurations.
Table A9-2 Supported features in the ACE configurations
Features Configuration
AXI mode ACE non-
coherent, no L3
cache
ACE non-
coherent, with L3
cache
ACE outer
coherent
ACE inner
coherent
AXI3 or AXI4 compliance Yes No No No No
ACE compliance No Yes Yes Yes Yes
Barriers on AR and AW channels
No No No No No
Cache maintenance requests on
AR channel
No No Yes Yes Yes
Snoops on AC channel No No No Yes Yes
Coherent requests on AR or AW
channel
No No No Yes Yes
DVM requests on AR channel No No No No Yes
A9 ACE Master Interface
A9.2 ACE configurations
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A9-115
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English