ARM Cortex-A35

Chapter A6
L1 Memory System
This chapter describes the L1 instruction cache and data cache.
It contains the following sections:
• A6.1 About the L1 memory system on page A6-90.
• A6.2 TLB Organization on page A6-91.
• A6.3 Program flow prediction on page A6-92.
• A6.4 About the internal exclusive monitor on page A6-93.
• A6.5 About data prefetching on page A6-95.
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A6-89
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