B1.110 Translation Table Base Control Register
The TTBCR characteristics are:
Purpose
Determines which of the Translation Table Base Registers defines the base address for a
translation table walk required for the stage 1 translation of a memory access from any mode
other than Hyp mode. Also controls the translation table format and, when using the Long-
descriptor translation table format, holds cacheability and shareability information.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
The processor does not use the implementation-defined bit, TTBCR[30], when using the Long-
descriptor translation table format, so this bit is RES0.
Configurations
TTBCR (NS) is architecturally mapped to AArch64 register TCR_EL1. See B2.94 Translation
Control Register, EL1 on page B2-536.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to TTBCR(S) is disabled when the CP15SDISABLE2
signal is asserted HIGH.
Attributes
TTBCR is a 32-bit register.
There are two formats for this register. TTBCR.EAE determines which format of the register is used.
B1 AArch32 system registers
B1.110 Translation Table Base Control Register
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B1-341
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