ARM Cortex-A35 User Manual

B2.82 Monitor Debug System Control Register, EL1
The MDSCR_EL1 characteristics are:
Purpose
Main control register for the debug implementation.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
MDSCR_EL1 is architecturally mapped to AArch32 register DBGDSCRext.
Attributes
MDSCR_EL1 is a 32-bit register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 15 14 13 12
RES0
11 7 6
RES0
5 1
SS
0
RES0
RXfull
TXfull
RES0
RXO
TXU
RES0
INTdis
TDA
RES0
RAZ/WI
ERR
TDCC
KDE
HDE
MDE
Figure B2-52 MDSCR_EL1 bit assignments
[31]
Reserved, RES0.
RXfull, [30]
Used for save/restore of EDSCR.RXfull
• When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must
treat it as UNK/SBZP.
• When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
TXfull, [29]
Used for save/restore of EDSCR.RXfull
• When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must
treat it as UNK/SBZP.
• When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW.
[28]
Reserved, RES0.
B2 AArch64 system registers
B2.82 Monitor Debug System Control Register, EL1
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B2-506
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English