[5:0]
Reserved, RES0.
To access the MDCR_EL3:
MRS <Xt>, MDCR_EL3 ; Read EL3 Monitor Debug Configuration Register
MSR MDCR_EL3, <Xt> ; Write EL3 Monitor Debug Configuration Register
Register access is encoded as follows:
Table B2-75 MDCR_EL3 access encoding
op0 op1 CRn CRm op2
11 110 0001 0011 001
B2 AArch64 system registers
B2.81 Monitor Debug Configuration Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-505
Non-Confidential
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