ARM Cortex-A35 User Manual

B2.80 Monitor Debug Configuration Register, EL2
The MDCR_EL2 characteristics are:
Purpose
Provides EL2 configuration options for self-hosted debug and the Performance Monitors
extension.
Usage constraints
This register is accessible as follows:
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
• MDCR_EL2 is architecturally mapped to AArch32 register HDCR. See B1.63 Hyp Debug
Control Register on page B1-248.
• If EL2 is not implemented, this register is RES0 from EL3.
Attributes
MDCR_EL2 is a 32-bit register.
31 11 10 9 8 7 6 5 4 0
RES0 HPMN
TDOSA
TDA
TDE
HPME
TPM
TPMCR
12
TDRA
Figure B2-50 MDCR_EL2 bit assignments
[31:12]
Reserved, RES0.
TDRA, [11]
Trap debug ROM address register access.
0 Has no effect on accesses to debug ROM address registers from EL1 and EL0.
1 Trap valid Non-secure EL1 and EL0 access to debug ROM address registers to Hyp mode.
When this bit is set to 1, any access to the following registers from EL1 or EL0 is trapped to
EL2:
• AArch32: DBGDRAR, DBGDSAR.
• AArch64: MDRAR_EL1.
If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is 1, then this bit is ignored and treated as though it
is 1 other than for the value read back from MDCR_EL2.
On Warm reset, the field resets to 0.
TDOSA, [10]
Trap Debug OS-related register access:
B2 AArch64 system registers
B2.80 Monitor Debug Configuration Register, EL2
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B2-500
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English