0 Has no effect on accesses to OS-related debug registers.
1 Trap valid Non-secure accesses to OS-related debug registers to EL2.
When this bit is set to 1, any access to the following registers from EL1 or EL0 is trapped to
EL2:
• AArch32: DBGOSLAR, DBGOSLSR, DBGOSDLR, DBGPRCR.
• AArch64: OSLAR_EL1, OSLSR_EL1, OSDLR_EL1, DBGPRCR_EL1.
If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is 1, then this bit is ignored and treated as though it
is 1 other than for the value read back from MDCR_EL2.
On Warm reset, the field resets to 0.
TDA, [9]
Trap Debug Access:
0 Has no effect on accesses to Debug registers.
1 Trap valid Non-secure accesses to Debug registers to EL2.
When this bit is set to 1, any valid Non-secure access to the debug registers from EL1 or EL0,
other than the registers trapped by the TDRA and TDOSA bits, is trapped to EL2.
If HCR_EL2.TGE is 1 or MDCR_EL2.TDE is1, then this bit is ignored and treated as though it
is 1 other than for the value read back from MDCR_EL2.
On Warm reset, the field resets to 0.
TDE, [8]
Trap software debug exceptions:
0 Has no effect on software debug exceptions.
1 Route Software debug exceptions from Non-secure EL1 and EL0 to EL2. Also enables traps
on all debug register accesses to EL2.
If HCR_EL2.TGE is 1, then this bit is ignored and treated as though it is 1 other than for the
value read back from MDCR_EL2.This bit resets to 0.
HPME, [7]
Hypervisor Performance Monitor Enable:
0 EL2 performance monitor counters disabled.
1 EL2 performance monitor counters enabled.
When this bit is set to 1, the Performance Monitors counters that are reserved for use from EL2
or Secure state are enabled. For more information see the description of the HPMN field.
The reset value of this bit is UNKNOWN.
TPM, [6]
Trap Performance Monitor accesses:
0 Has no effect on performance monitor accesses.
1 Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not
UNALLOCATED to EL2.
This bit resets to 0.
TPMCR, [5]
Trap PMCR_EL0 accesses:
0 Has no effect on PMCR_EL0 accesses.
B2 AArch64 system registers
B2.80 Monitor Debug Configuration Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-501
Non-Confidential
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