B1.103 Reset Management Register
The RMR characteristics are:
Purpose
Controls the execution state that the processor boots into and allows request of a warm reset.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - - RW RW
Configurations
The RMR is architecturally mapped to the AArch64 RMR_EL3 register. See B2.87 Reset
Management Register, EL3 on page B2-519.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
RMR is a 32-bit register.
31
0
RES0
12
AA64
RR
Figure B1-56 RMR bit assignments
[31:2]
Reserved, RES0.
RR, [1]
Reset Request. The possible values are:
0 This is the reset value.
1 Requests a warm reset. This bit is set to 0 by either a cold or warm reset.
The bit is strictly a request.
The RR bit drives the WARMRSTREQ output signal.
AA64, [0]
Determines which execution state the processor boots into after a warm reset. The possible
values are:
0 AArch32 Execution state.
1 AArch64 Execution state.
The reset vector address on reset takes a choice between two values, depending on the value in
the AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to
change the reset vector to go to a different location.
The cold reset value depends on the AA64nAA32 signal.
B1 AArch32 system registers
B1.103 Reset Management Register
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B1-326
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