ARM Cortex-A35 User Manual

C7.2 Debug Breakpoint Control Registers, EL1
The DBGBCRn_EL1characteristics are:
Purpose
Holds control information for a breakpoint. Each DBGBVR_EL1 is associated with a
DBGBCR_EL1 to form a Breakpoint Register Pair (BRP). DBGBVRn_EL1 is associated with
DBGBCRn_EL1 to form BRPn.
The range of n for DBGBCRn_EL1 is 0 to 5.
Usage constraints
These registers are accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Configurations
DBGBCRn_EL1 are architecturally mapped to:
• The AArch32 DBGBCRn registers. See C6.2 Debug Breakpoint Control Registers
on page C6-622.
• The external DBGBCRn_EL1 registers.
Attributes
See C7.1 AArch64 debug register summary on page C7-634.
The debug logic reset value of a DBGBCRn_EL1 is UNKNOWN.
31 24 23 20 19 16 15 13 9 8 5 4 3 2 1 0
LBN RES0SSC
12
HMC
14
BT BAS PMC ERES0 RES0
Figure C7-1 DBGBCRn_EL1
[31:24]
Reserved, RES0.
BT, [23:20]
Breakpoint Type. This field controls the behavior of Breakpoint debug event generation. This
includes the meaning of the value held in the associated DBGBVRn_EL1, indicating whether it
is an instruction address match or mismatch or a Context match. It also controls whether the
breakpoint is linked to another breakpoint. The possible values are:
0b0000 Unlinked instruction address match.
0b0001 Linked instruction address match.
0b0010 Unlinked Context ID match.
0b0011 Linked Context ID match.
0b0100 Unlinked instruction address mismatch.
0b0101 Linked instruction address mismatch.
0b1000 Unlinked VMID match.
0b1001 Linked VMID match.
C7 AArch64 debug registers
C7.2 Debug Breakpoint Control Registers, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English