ARM Cortex-A35 User Manual

0b1010 Unlinked VMID + Context ID match.
0b1011 Linked VMID + Context ID match.
All other values are reserved.
The field break down is:
• BT[3:1]: Base type. If the breakpoint is not context-aware, these bits are RES0. Otherwise, the
possible values are:
0b000 Match address. DBGBVRn_EL1 is the address of an instruction.
0b001 Match context ID. DBGBVRn_EL1[31:0] is a context ID.
0b010 Address mismatch. Mismatch address. Behaves as type 0b000 if either:
— In an AArch64 translation regime.
— Halting debug-mode is enabled and halting is allowed.
Otherwise, DBGBVRn_EL1 is the address of an instruction to be stepped.
0b100 Match VMID. DBGBVRn_EL1[39:32] is a VMID.
0b101 Match VMID and context ID. DBGBVRn_EL1[31:0] is a context ID, and
DBGBVRn_EL1[39:32] is a VMID.
• BT[0]: Enable linking.
LBN, [19:16]
Linked breakpoint number. For Linked address matching breakpoints, this specifies the index of
the Context-matching breakpoint linked to.
SSC, [15:14]
Security State Control. Determines the security states that a breakpoint debug event for
breakpoint n is generated.
This field must be interpreted with the Higher Mode Control (HMC), and Privileged Mode
Control (PMC), fields to determine the mode and security states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the fields.
HMC, [13]
Hyp Mode Control bit. Determines the debug perspective for deciding when a breakpoint debug
event for breakpoint n is generated.
This bit must be interpreted with the SSC and PMC fields to determine the mode and security
states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the fields.
[12:9]
Reserved, RES0.
BAS, [8:5]
Byte Address Select. Defines which half-words a regular breakpoint matches, regardless of the
instruction set and execution state. A debugger must program this field as follows:
0x3 Match the T32 instruction at DBGBVRn_EL1.
0xC Match the T32 instruction at DBGBVRn+2_EL1.
0xF Match the A64 or A32 instruction at DBGBVRn_EL1, or context match.
All other values are reserved.
C7 AArch64 debug registers
C7.2 Debug Breakpoint Control Registers, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English