The Armv8-A architecture does not support direct execution of Java bytecodes. BAS[3] and
BAS[1] ignore writes and on reads return the values of BAS[2] and BAS[0] respectively.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information on how the BAS field is interpreted by hardware.
[4:3]
Reserved, RES0.
PMC, [2:1]
Privileged Mode Control. Determines the exception level or levels that a breakpoint debug event
for breakpoint n is generated.
This field must be interpreted with the SSC and HMC fields to determine the mode and security
states that can be tested.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for
possible values of the fields.
Bits[2:1] have no effect for accesses made in Hyp mode.
E, [0]
Enable breakpoint. This bit enables the BRP:
0 BRP disabled.
1 BRP enabled.
A BRP never generates a breakpoint debug event when it is disabled.
The value of DBGBCRn_EL1.E is UNKNOWN on reset. A debugger must ensure that
DBGBCRn_EL1.E has a defined value before it enables debug.
To access the DBGBCRn_EL1 in AArch64 Execution state, read or write the register with:
MRS <Xt>, DBGBCRn_EL1; Read Debug Breakpoint Control Register nMSR DBGBCRn_EL1, <Xt>; Write
Debug Breakpoint Control Register n
To access the DBGBCRn_EL1 in AArch32 Execution state, read or write the CP14 register with:
MRC p14, 0, <Rt>, c0, cn, 4; Read Debug Breakpoint Control Register nMCR p14, 0, <Rt>, c0,
cn, 4; Write Debug Breakpoint Control Register n
The DBGBCRn_EL1 can be accessed through the external debug interface, offset 0x4n8. The range of
bits for DBGBCRn_EL1 is 0 to 5.
C7 AArch64 debug registers
C7.2 Debug Breakpoint Control Registers, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C7-638
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