C7.1 AArch64 debug register summary
This section summarizes the debug control registers that are accessible in the AArch64 Execution state.
These registers, listed in the following table, are accessed by the MRS and MSR instructions in the order of
Op0, CRn, Op1, CRm, Op2.
See C8.1 Memory-mapped debug register summary on page C8-644 for a complete list of registers
accessible from the external debug interface. The 64-bit registers cover two addresses on the external
memory interface. For those registers not described in this chapter, see the Arm
®
Architecture Reference
Manual Armv8, for Armv8-A architecture profile.
Table C7-1 AArch64 debug register summary
Name Type Reset Width Description
OSDTRRX_EL1 RW - 32 Debug Data Transfer Register, Receive, External View
DBGBVR0_EL1 RW - 64 Debug Breakpoint Value Register 0
DBGBCR0_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
DBGWVR0_EL1 RW - 64 Debug Watchpoint Value Register 0
DBGWCR0_EL1 RW - 32 C7.3 Debug Watchpoint Control Registers, EL1
on page C7-639
DBGBVR1_EL1 RW - 64 Debug Breakpoint Value Register 1
DBGBCR1_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
DBGWVR1_EL1 RW - 64 Debug Watchpoint Value Register 1
DBGWCR1_EL1 RW - 32 C7.3 Debug Watchpoint Control Registers, EL1
on page C7-639
MDCCINT_EL1 RW
0x00000000
32 Monitor Debug Comms Channel Interrupt Enable Register
MDSCR_EL1 RW - 32 B2.82 Monitor Debug System Control Register, EL1
on page B2-506
DBGBVR2_EL1 RW - 64 Debug Breakpoint Value Register 2
DBGBCR2_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
DBGWVR2_EL1 RW - 64 Debug Watchpoint Value Register 2
DBGWCR2_EL1 RW - 32 C7.3 Debug Watchpoint Control Registers, EL1
on page C7-639
OSDTRTX_EL1 RW - 32 Debug Data Transfer Register, Transmit, External View
DBGBVR3_EL1 RW - 64 Debug Breakpoint Value Register 3
DBGBCR3_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
DBGWVR3_EL1 RW - 64 Debug Watchpoint Value Register 3
DBGWCR3_EL1 RW - 32 C7.3 Debug Watchpoint Control Registers, EL1
on page C7-639
DBGBVR4_EL1 RW - 64 Debug Breakpoint Value Register 4
C7 AArch64 debug registers
C7.1 AArch64 debug register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C7-634
Non-Confidential
To Next Page
Loading...
Need help?
General
