Translation table walk disable for translations using TTBR0_EL1. Controls whether a
translation table walk is performed on a TLB miss for an address that is translated using
TTBR0_EL1. The possible values are:
0 Perform translation table walk using TTBR0_EL1.
1 A TLB miss on an address translated from TTBR0_EL1 generates a Translation fault.
No translation table walk is performed.
[6]
Reserved, RES0.
T0SZ, [5:0]
Size offset of the memory region addressed by TTBR0_EL1. The region size is 2
(64-T0SZ)
bytes.
To access the TCR_EL1:
MRS <Xt>, TCR_EL1 ; Read TCR_EL1 into Xt
MSR TCR_EL1, <Xt> ; Write Xt to TCR_EL1
Register access is encoded as follows:
Table B2-87 TCR_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0010 0000 010
B2 AArch64 system registers
B2.94 Translation Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-539
Non-Confidential
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