Translation table walk disable for translations using TTBR1_EL1. Controls whether a
translation table walk is performed on a TLB miss for an address that is translated using
TTBR1_EL1. The possible values are:
0 Perform translation table walk using TTBR1_EL1.
1 A TLB miss on an address translated from TTBR1_EL1 generates a Translation fault.
No translation table walk is performed.
A1, [22]
Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The possible values are:
0 TTBR0_EL1.ASID defines the ASID.
1 TTBR1_EL1.ASID defines the ASID.
T1SZ, [21:16]
Size offset of the memory region addressed by TTBR1_EL1. The region size is 2
(64-T1SZ)
bytes.
TG0, [15:14]
TTBR0_EL1 granule size. The possible values are:
0b00 4KB.
0b10 16KB.
0b01 64KB.
0b11 Reserved.
All other values are not supported.
SH0, [13:12]
Shareability attribute for memory associated with translation table walks using TTBR0_EL1.
The possible values are:
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer shareable.
0b11 Inner shareable.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL1. The possible values are:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL1. The possible values are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
EPD0, [7]
B2 AArch64 system registers
B2.94 Translation Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-538
Non-Confidential
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