ARM Cortex-A35 User Manual

0 8-bit.
1 16-bit.
[35]
Reserved, RES0.
IPS, [34:32]
Intermediate Physical Address Size. The possible values are:
0b000 32 bits, 4GB.
0b001 36 bits, 64GB.
0b010 40 bits, 1TB.
All other values are reserved.
TG1, [31:30]
TTBR1_EL1 granule size. The possible values are:
0b00 Reserved.
0b10 4KB.
0b01 16KB.
0b11 64KB.
All other values are not supported.
SH1, [29:28]
Shareability attribute for memory associated with translation table walks using TTBR1_EL1.
The possible values are:
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer shareable.
0b11 Inner shareable.
ORGN1, [27:26]
Outer cacheability attribute for memory associated with translation table walks using
TTBR1_EL1. The possible values are:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN1, [25:24]
Inner cacheability attribute for memory associated with translation table walks using
TTBR1_EL1. The possible values are:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
EPD1, [23]
B2 AArch64 system registers
B2.94 Translation Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-537
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English