ARM Cortex-A35 User Manual

0x2 Supported branch predictor maintenance operations are:
• Invalidate all branch predictors.
• Invalidate branch predictors by MVA.
CMaintSW, [7:4]
Cache maintenance by set/way. Indicates the supported cache maintenance operations by set/
way.
0x1 Supported hierarchical cache maintenance operations by set/way are:
• Invalidate data cache by set/way.
• Clean data cache by set/way.
• Clean and invalidate data cache by set/way.
CMaintVA, [3:0]
Cache maintenance by MVA. Indicates the supported cache maintenance operations by MVA.
0x1 Supported hierarchical cache maintenance operations by MVA are:
• Invalidate data cache by MVA.
Invalidate data cache by MVA operations are treated as clean and invalidate data
cache by MVA operations on the executing core. If the operation is broadcast to
another core then it is broadcast as an invalidate data cache by MVA operation.
• Clean data cache by MVA.
• Clean and invalidate data cache by MVA.
• Invalidate instruction cache by MVA.
• Invalidate all instruction cache entries.
To access the ID_MMFR3_EL1:
MRS <Xt>, ID_MMFR3_EL1 ; Read ID_MMFR3_EL1 into Xt
Register access is encoded as follows:
Table B2-58 ID_MMFR3_EL1 access encoding
op0 op1 CRn CRm op2
11 000 0000 0001 111
B2 AArch64 system registers
B2.66 AArch32 Memory Model Feature Register 3, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-474
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English