ARM Cortex-A35

Table C8-1 Memory-mapped debug register summary (continued)
Offset Name Type Width Description
0xFEC
EDPIDR3 RO 32 C8.12 External Debug Peripheral Identification Register 3
on page C8-661
0xFF0
EDCIDR0 RO 32 C8.16 External Debug Component Identification Register 0
on page C8-665
0xFF4
EDCIDR1 RO 32 C8.17 External Debug Component Identification Register 1
on page C8-666
0xFF8
EDCIDR2 RO 32 C8.18 External Debug Component Identification Register 2
on page C8-667
0xFFC
EDCIDR3 RO 32 C8.19 External Debug Component Identification Register 3
on page C8-668
C8 Memory-mapped debug registers
C8.1 Memory-mapped debug register summary
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