SED, [8]
SETEND Disable:
0 The SETEND instruction is available.
1 The SETEND instruction is UNALLOCATED.
ITD, [7]
IT Disable:
0 The IT instruction functionality is available.
1 All encodings of the IT instruction with hw1[3:0]!=1000 are UNDEFINED and treated as
unallocated. All encodings of the subsequent instruction with the following values for hw1
are UNDEFINED (and treated as unallocated):
11xxxxxxxxxxxxxx All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store
multiple
1x11xxxxxxxxxxxx Miscellaneous 16-bit instructions
1x100xxxxxxxxxx ADD Rd, PC, #imm
01001xxxxxxxxxxx LDR Rd, [PC, #imm]
0100x1xxx1111xxx ADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111 ADD(4),CMP(3), MOV
[6]
Reserved, RES0.
CP15BEN, [5]
CP15 barrier enable:
0 CP15 barrier operations disabled. Their encodings are UNDEFINED.
1 CP15 barrier operations enabled.
[4:3]
Reserved, RES1.
C, [2]
Cache enable. This is an enable bit for data and unified caches at EL2:
0 Data and unified caches disabled at EL2.
1 Data and unified caches enabled at EL2.
When this bit is 0, all EL2 Normal memory data accesses and all accesses to the EL2 translation
tables are Non-cacheable.
If this register is at the highest exception level implemented, field resets to 0. Otherwise, its
reset value is UNKNOWN.
A, [1]
Alignment check enable. This is the enable bit for Alignment fault checking:
0 Alignment fault checking disabled.
1 Alignment fault checking enabled.
When this bit is 1, all instructions that load or store one or more registers, other than load/store
exclusive and load-acquire/store-release, have an alignment check that the address being
accessed is aligned to the size of the data element(s) being accessed. If this check fails it causes
an Alignment fault, that is taken as a Data Abort exception.
B1 AArch32 system registers
B1.67 Hyp System Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-256
Non-Confidential
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