ARM Cortex-A35 User Manual

1 Big endian.
[24]
Reserved, RES0.
[23:22]
Reserved, RES1.
FI, [21]
Fast Interrupts configuration enable bit. This bit can be used to reduce interrupt latency by
disabling implementation-defined performance features.
This bit is not implemented, RES0.
[20]
Reserved, RES0.
WXN, [19]
Write permission implies Execute Never (XN). This bit can be used to require all memory
regions with write permission to be treated as XN:
0 Regions with write permission are not forced to XN.
1 Regions with write permission are forced to XN.
The WXN bit is permitted to be cached in a TLB.
[18]
Reserved, RES1.
[17]
Reserved, RES0.
[16]
Reserved, RES1.
[15:13]
Reserved, RES0.
I, [12]
Instruction cache enable. This is an enable bit for instruction caches at EL2:
0 Instruction caches disabled at EL2. If HSCTLR.M is set to 0, instruction accesses from
stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner
Non-cacheable, Outer Non-cacheable.
1 Instruction caches enabled at EL2. If HSCTLR.M is set to 0, instruction accesses from
stage 1 of the EL2 translation regime are to Normal memory, Outer Shareable, Inner
Write-Through, Outer Write-Through.
When this bit is 0, all EL2 Normal memory instruction accesses are Non-cacheable.
If this register is at the highest exception level implemented, field resets to 0. Otherwise, its
reset value is UNKNOWN.
[11]
Reserved, RES1.
[10:9]
Reserved, RES0.
B1 AArch32 system registers
B1.67 Hyp System Control Register
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reserved.
B1-255
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English