ARM Cortex-A35 User Manual

WXN, [19]
Force treatment of all memory regions with write permissions as XN. The possible values are:
0 Regions with write permissions are not forced XN. This is the reset value.
1 Regions with write permissions are forced XN.
[18]
Reserved, RES1.
[17]
Reserved, RES0.
[16]
Reserved, RES1.
[15:13]
Reserved, RES0.
I, [12]
Global instruction cache enable. The possible values are:
0 Instruction caches disabled. This is the reset value.
1 Instruction caches enabled.
[11]
Reserved, RES1.
[10:6]
Reserved, RES0.
[5:4]
Reserved, RES1.
SA, [3]
Enables stack alignment check. The possible values are:
0 Disables stack alignment check.
1 Enables stack alignment check. This is the reset value.
C, [2]
Global enable for data and unifies caches. The possible values are:
0 Disables data and unified caches. This is the reset value.
1 Enables data and unified caches.
A, [1]
Enable alignment fault check The possible values are:
0 Disables alignment fault checking. This is the reset value.
1 Enables alignment fault checking.
M, [0]
Global enable for the EL3 MMU. The possible values are:
0 Disables EL3 MMU. This is the reset value.
1 Enables EL3 MMU.
B2 AArch64 system registers
B2.92 System Control Register, EL3
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English