TWI, [12]
Trap WFI instructions. The possible values are:
0 WFI instructions are not trapped. This is the reset value.
1 WFI instructions executed in any mode other than Monitor mode are trapped to Monitor mode
as UNDEFINED if the instruction would otherwise cause suspension of execution.
[11:10]
Reserved, RES0.
SIF, [9]
Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction
fetches from Non-secure memory. The possible values are:
0 Secure state instruction fetches from Non-secure memory permitted. This is the reset value.
1 Secure state instruction fetches from Non-secure memory not permitted.
HCE, [8]
Hyp Call enable. This bit enables use of the HVC instruction from Non-secure EL1 modes. The
possible values are:
0 The HVC instruction is UNDEFINED in any mode. This is the reset value.
1 The HVC instruction enabled in Non-secure EL1, and performs a Hyp Call.
SCD, [7]
Secure Monitor Call disable. Makes the SMC instruction UNDEFINED in Non-secure state. The
possible values are:
0 SMC executes normally in Non-secure state, performing a Secure Monitor Call. This is the
reset value.
1 The SMC instruction is UNDEFINED in Non-secure state.
A trap of the SMC instruction to Hyp mode takes priority over the value of this bit.
nET, [6]
Not Early Termination. This bit disables early termination.
This bit is not implemented, RES0.
AW, [5]
A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state.
• CPSR.A can be modified only in Secure state. This is the reset value.
• CPSR.A can be modified in any security state.
FW, [4]
F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state:
• CPSR.F can be modified only in Secure state. This is the reset value.
• CPSR.F can be modified in any security state.
EA, [3]
External Abort handler. This bit controls which mode takes external aborts. The possible values
are:
0 External aborts taken in abort mode. This is the reset value.
1 External aborts taken in Monitor mode.
FIQ, [2]
B1 AArch32 system registers
B1.104 Secure Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-329
Non-Confidential
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