FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
0 FIQs taken in FIQ mode. This is the reset value.
1 FIQs taken in Monitor mode.
IRQ, [1]
IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
0 IRQs taken in IRQ mode. This is the reset value.
1 IRQs taken in Monitor mode.
NS, [0]
Non-secure bit. Except when the processor is in Monitor mode, this bit determines the security
state of the processor. The possible values are:
0 Processor is in secure state. This is the reset value.
1 Processor is in non-secure state.
To access the SCR:
MRC p15,0,<Rt>,c1,c1,0 ; Read SCR into Rt
MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR
Register access is encoded as follows:
Table B1-89 SCR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0001 000
B1 AArch32 system registers
B1.104 Secure Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-330
Non-Confidential
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