ARM Cortex-A35 User Manual

0b111 512 Architectural Timer ticks are required before retention entry.
This field is present only if the Advanced SIMD and floating-point support is implemented.
Otherwise, it is RES0.
CPURETCTL, [2:0]
CPU retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
0b100 64 Architectural Timer ticks are required before retention entry.
0b101 128 Architectural Timer ticks are required before retention entry.
0b110 256 Architectural Timer ticks are required before retention entry.
0b111 512 Architectural Timer ticks are required before retention entry.
To access the CPUECTLR:
MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register
MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register
Register access is encoded as follows:
Table B1-37 CPUECTLR access encoding
coproc opc1 CRm
1111 0001 1111
B1 AArch32 system registers
B1.43 CPU Extended Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English