IT Disable:
0 The IT instruction functionality is available.
1 All encodings of the IT instruction with hw1[3:0]!=1000 are UNDEFINED and treated as
unallocated. All encodings of the subsequent instruction with the following values for
hw1 are UNDEFINED (and treated as unallocated):
11xxxxxxxxxxxxxx All 32-bit instructions, B(2), B(1), Undefined, SVC, Load/Store
multiple
1x11xxxxxxxxxxxx Miscellaneous 16-bit instructions
1x100xxxxxxxxxxx ADD Rd, PC, #imm
01001xxxxxxxxxxx LDR Rd, [PC, #imm]
0100x1xxx1111xxx ADD(4),CMP(3), MOV, BX pc, BLX pc
010001xx1xxxx111 ADD(4),CMP(3), MOV
THEE, [6]
Reserved, RES0.
CP15BEN, [5]
CP15 barrier enable.
0 CP15 barrier operations disabled. Their encodings are UNDEFINED.
1 CP15 barrier operations enabled.
[4:3]
Reserved, RES1.
C, [2]
Cache enable. This is a global enable bit for data and unified caches:
0 Data and unified caches disabled, this is the reset value.
1 Data and unified caches enabled.
A, [1]
Alignment check enable. This is the enable bit for Alignment fault checking:
0 Alignment fault checking disabled, this is the reset value.
1 Alignment fault checking enabled.
M, [0]
MMU enable. This is a global enable bit for the MMU stage 1 address translation:
0 EL1 and EL0 stage 1 MMU disabled.
1 EL1 and EL0 stage 1 MMU enabled.
To access the SCTLR:
MRC p15, 0, <Rt>, c1, c0, 0 ; Read SCTLR into Rt
MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR
Register access is encoded as follows:
Table B1-90 SCTLR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0000 000
B1 AArch32 system registers
B1.105 System Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-334
Non-Confidential
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