ARM Cortex-A35 User Manual

0 Regions with write permission are not forced to be XN, this is the reset value.
1 Regions with write permissions are forced to be XN.
nTWE, [18]
Not trap WFE.
0 If a WFE instruction executed at EL0 would cause execution to be suspended, such as
if the event register is not set and there is not a pending WFE wakeup event, it is taken
as an exception to EL1 using the 0x1 ESR code.
1 WFE instructions are executed as normal.
[17]
Reserved, RES0.
nTWI, [16]
Not trap WFI.
0 If a WFI instruction executed at EL0 would cause execution to be suspended, such as
if there is not a pending WFI wakeup event, it is taken as an exception to EL1 using
the 0x1 ESR code.
1 WFI instructions are executed as normal.
[15:14]
Reserved, RES0.
V, [13]
Vectors bit. This bit selects the base address of the exception vectors:
0 Normal exception vectors, base address 0x00000000. Software can remap this base address
using the VBAR.
1 High exception vectors, base address 0xFFFF0000. This base address is never remapped.
The input VINITHI defines the reset value of the V bit.
I, [12]
Instruction cache enable bit. This is a global enable bit for instruction caches:
0 Instruction caches disabled. If SCTLR.M is set to 0, instruction accesses from stage 1
of the EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner
Non-cacheable, Outer Non-cacheable.
1 Instruction caches enabled. If SCTLR.M is set to 0, instruction accesses from stage 1
of the EL0/EL1 translation regime are to Normal memory, Outer Shareable, Inner
Write-Through, Outer Write-Through.
[11]
Reserved, RES1
[10:9]
Reserved, RES0
SED, [8]
SETEND Disable:
0 The SETEND instruction is available.
1 The SETEND instruction is UNALLOCATED.
ITD, [7]
B1 AArch32 system registers
B1.105 System Control Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English