SPME, [17]
Secure performance monitors enable. This allows event counting in Secure state:
0 Event counting prohibited in Secure state, unless overridden by the authentication interface.
This is the reset value.
1 Event counting allowed in Secure state.
[16]
Reserved, RES0.
SPD, [15:14]
AArch32 secure privileged debug. Enables or disables debug exceptions in Secure state, other
than Software breakpoint instructions. The possible values are:
0b00 Legacy mode. Debug exceptions from Secure EL1 are enabled by the authentication
interface.
0b10 Secure privileged debug disabled. Debug exceptions from Secure EL1 are disabled.
0b11 Secure privileged debug enabled. Debug exceptions from Secure EL1 are enabled.
The value 0b01 is reserved.
If debug exceptions from Secure EL1 are enabled, then debug exceptions from Secure EL0 are
also enabled.
Otherwise, debug exceptions from Secure EL0 are enabled only if SDER32_EL3.SUIDEN is 1.
SPD is ignored in Non-secure state. Debug exceptions from Software breakpoint instruction
debug events are always enabled.
[13:0]
Reserved, RES0.
To access the SDCR:
MRC p15,0,<Rt>,c1,c3,1 ; Read SDCR into Rt
MCR p15,0,<Rt>,c1,c3,1 ; Write Rt to SDCR
Register access is encoded as follows:
Table B1-91 SDCR access encoding
coproc opc1 CRn CRm opc2
1111 000 0001 0011 001
B1 AArch32 system registers
B1.106 Secure Debug Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-336
Non-Confidential
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