0 Does not cause any instruction to be trapped.This is the reset value if the Advanced SIMD
and floating-point support is implemented.
1 Causes any instructions that use the registers associated with Advanced SIMD or floating-
point execution to be trapped. This is always the value if the Advanced SIMD and floating-
point support is not implemented.
[9:0]
Reserved, RES0.
To access the CPTR_EL3:
MRS <Xt>, CPTR_EL3 ; Read CPTR_EL3 into Xt
MSR CPTR_EL3, <Xt> ; Write Xt to CPTR_EL3
B2 AArch64 system registers
B2.33 Architectural Feature Trap Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-407
Non-Confidential
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