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ARM Cortex-A35 User Manual

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Register access is encoded as follows:
Table B2-25 CSSELR_EL1 access encoding
op0 op1 CRn CRm op2
11 010 0000 0001 000
B2 AArch64 system registers
B2.34 Cache Size Selection Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-409
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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