ARM Cortex-A35 User Manual

Table B1-11 c8 System operations summary (continued)
op1 CRm op2 Name Description
4 c0 1
TLBIIPAS2IS
TLB Invalidate entry by Intermediate Physical Address, Stage 2, Inner Shareable
5
TLBIIPAS2LIS
TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level, Inner Shareable
c3 0
TLBIALLHIS
Invalidate entire Hyp unified TLB Inner Shareable
1
TLBIMVAHIS
Invalidate Hyp unified TLB entry by VA Inner Shareable
4
TLBIALLNSNHIS
Invalidate entire Non-secure non-Hyp unified TLB Inner Shareable
5
TLBIMVALHIS
Invalidate Unified Hyp TLB entry by VA Inner Shareable, Last level
c4 1
TLBIIPAS2
TLB Invalidate entry by Intermediate Physical Address, Stage 2
5
TLBIIPAS2L
TLB Invalidate entry by Intermediate Physical Address, Stage 2, Last level
c7 0
TLBIALLH
Invalidate entire Hyp unified TLB
1
TLBIMVAH
Invalidate Hyp unified TLB entry by VA
4
TLBIALLNSNH
Invalidate entire Non-secure non-Hyp unified TLB
5
TLBIMVALH
Invalidate Unified Hyp TLB entry by VA, Last level
B1 AArch32 system registers
B1.11 c8 system operations
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English