ARM Cortex-A35 User Manual

0 Has no effect on accesses to CP14 Debug registers.
1 Trap valid Non-secure accesses to CP14 OS-related Debug registers to Hyp mode.
When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debug
registers is trapped to Hyp mode:
• DBGOSLSR.
• DBGOSLAR.
• DBGOSDLR.
• DBGPRCR.
If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other
than for the value read back from HDCR.
On Warm reset, the field resets to 0.
TDA, [9]
Trap Debug Access:
0 Has no effect on accesses to CP14 Debug registers.
1 Trap valid Non-secure accesses to CP14 Debug registers to Hyp mode.
When this bit is set to 1, any valid access to the CP14 Debug registers, other than the registers
trapped by the TDRA and TDOSA bits, is trapped to Hyp mode.
If HCR.TGE is 1 or HDCR.TDE is1, then this bit is ignored and treated as though it is 1 other
than for the value read back from HDCR.
On Warm reset, the field resets to 0.
TDE, [8]
Trap Debug Exceptions:
0 Has no effect on Debug exceptions.
1 Route Non-secure Debug exceptions to Hyp mode.
When this bit is set to 1, any Debug exception taken in Non-secure state is trapped to Hyp mode.
If HCR.TGE is 1, then this bit is ignored and treated as though it is 1 other than for the value
read back from HDCR.This bit resets to 0.
HPME, [7]
Hypervisor Performance Monitor Enable:
0 Hyp mode performance monitor counters disabled.
1 Hyp mode performance monitor counters enabled.
When this bit is set to 1, access to the performance monitors that are reserved for use from Hyp
mode is enabled. For more information, see the description of the HPMN field.
The reset value of this bit is UNKNOWN.
TPM, [6]
Trap Performance Monitor accesses:
0 Has no effect on performance monitor accesses.
1 Trap valid Non-secure performance monitor accesses to Hyp mode.
When this bit is set to 1, any valid Non-secure access to the Performance Monitor registers is
trapped to Hyp mode. This bit resets to 0. See the Arm
®
Architecture Reference Manual Armv8,
for Armv8-A architecture profile for more information.
TPMCR, [5]
B1 AArch32 system registers
B1.63 Hyp Debug Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-249
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English