Bit[17] Exception level 1.
Bit[18] RAZ/WI. Instruction tracing is not implemented for exception level 2.
Bit[19] Exception level 3.
[15:12]
Reserved, RES0.
TRCERR, [11]
Selects whether a system error exception must always be traced:
0 System error exception is traced only if the instruction or exception immediately
before the system error exception is traced.
1 System error exception is always traced regardless of the value of ViewInst.
TRCRESET, [10]
Selects whether a reset exception must always be traced:
0 Reset exception is traced only if the instruction or exception immediately before the
reset exception is traced.
1 Reset exception is always traced regardless of the value of ViewInst.
SSSTATUS, [9]
Indicates the current status of the start/stop logic:
0 Start/stop logic is in the stopped state.
1 Start/stop logic is in the started state.
[8]
Reserved, RES0.
TYPE, [7]
Selects the resource type for the viewinst event:
0 Single selected resource.
1 Boolean combined resource pair.
[6:4]
Reserved, RES0.
SEL, [3:0]
Selects the resource number to use for the viewinst event, based on the value of TYPE:
When TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0].
When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].
The TRCVICTLR can be accessed through the external debug interface, offset 0x080.
C11 ETM registers
C11.14 ViewInst Main Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C11-752
Non-Confidential
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