A.4 Reset signals
The processor uses a set of reset signals.
Table A-3 Reset and reset control signals
Signal Direction Description
nCPUPORESET[CN:0] Input
Processor powerup reset:
0
Apply reset to all processor logic.
1
Do not apply reset to all processor logic.
Processor logic includes Advanced SIMD and floating-point, debug, ETM trace unit,
breakpoint and watchpoint logic.
nCORERESET[CN:0] Input
Individual core resets excluding debug and ETM trace unit:
0
Apply reset to processor logic.
1
Do not apply reset to processor logic.
nPRESETDBG Input See A.15 APB interface signals on page Appx-A-873.
nL2RESET Input
L2 memory system reset:
0
Apply reset to the shared L2 memory system controller.
1
Do not apply reset to the shared L2 memory system controller.
nMBISTRESET Input See A.21 MBIST interface signals on page Appx-A-879.
L2RSTDISABLE Input
Disable the automatic invalidation of the L2 cache at reset:
0
Hardware resets the L2 cache.
1
Hardware does not reset the L2 cache.
This signal is sampled only during processor reset.
WARMRSTREQ[CN:0] Output
Request for a processor warm reset:
0
Do not apply warm reset.
1
Apply warm reset.
DBGRSTREQ[CN:0] Output Warm reset request.
DBGL1RSTDISABLE Input
Disable the automatic invalidation of the L1 data cache at processor reset:
0
Enable automatic invalidation of L1 data cache on reset.
1
Disable automatic invalidation of L1 data cache on reset.
This signal is sampled only during processor reset.
Related information
A3.3 Resets on page A3-52
A Signal Descriptions
A.4 Reset signals
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
Appx-A-851
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